data brief for further information contact your local stmicroelectronics sales office. september 2009 doc id 14449 rev 2 1/4 4 STEVAL-ISA044V2 3 a synchronous 900 khz step-down dc-dc converter with inhibit function based on the st1s10 features input voltage range: 2.5 v to 18 v max i out : 3 a high internal switching frequency : 900 khz pwm mode operation with a fixed frequency or synchronized to an external frequency between 400 khz and 1.2 mhz inhibit pin available quiescent current : < 6 a in inhibit state description the st1s10 is a step-down dc-dc converter with inhibit function optimized for powering high voltages in lcd applications and low voltage, digital core hdd applications. it replaces the high current linear solution when high power dissipation is a problem. it provides up to 3 a over an input voltage range of 2.5 v to 18 v, and synchronous rectification removes the need for an external schottky diode. a high internal switching frequency (900 khz) allows for the use of tiny surface-mount components, as well as the resistor divider to set the output voltage value. only an inductor and 3 capacitors are required. the current mode pwm architecture and stable operation with low-esr smd ceramic capacitors result in low output ripple. to maximize power conversion efficiency in light load, the regulator can work in burst mode automatically. the device can operate in pwm mode with a fixed frequency or synchronized to an external frequency. it switches at a frequency of 900 khz when the sync pin is connected to ground or a fixed voltage (less than 5.5 v), and can synchronize the switching frequency between 400 khz to 1.2 mhz from external clock that is applied to sync pin. a thermal shutdown circuit is integrated and activates at 150 c. cycle-by-cycle current limitation provides protection against shorted outputs. the quiescent current is less than 6 a in inhibit state. the device is available in mlp4x4 and so-8 epad packages. STEVAL-ISA044V2 www.st.com
circuit schematic STEVAL-ISA044V2 2/4 doc id 14449 rev 2 1 circuit schematic figure 1. schematic 6 3 7 l 1 ic i c 1 c 1 1 3 2 cn c n 2 r 2 r 1 1 c 2 r 3 c 3 2 5 4 - 8 gn g n d vou v o u t syn s y n c vi v i n vi v i n gn g n d gn g n d gn g n d vou v o u t 2-3=inh-of 2 - 3 = i n h - o f f 1-2=inh-o 1 - 2 = i n h - o n cn c n 3 cn c n 4 cn c n 1
STEVAL-ISA044V2 revision history doc id 14449 rev 2 3/4 2 revision history table 1. document revision history date revision changes 11-feb-2008 1 initial release. 01-sep-2009 2 updated figure on cover page
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